1. Field of the Invention
The invention in general relates to the fabrication of integrated circuits utilizing metal oxides, such as barium strontium titanate, and more particularly to the fabrication of thin film capacitors on silicon germanium substrates.
2. Statement of the Problem
Metal oxide materials, such as barium strontium titanate, commonly referred to as BST, are known to be useful in making Integrated circuit thin film capacitors having high dielectric constants. See, for example, Kuniaki Koyama et al., xe2x80x9cA Stacked Capacitor With (BaxSr1-x)TiO3 For 256M DRAMxe2x80x9d in IDEM (International Electron Devices Meeting) Technical Digest, December 1991, pp. 32.1.1-32.1.4; and U.S. Pat. No. 5,122,923 issued to Shogo Matsubara et al. In both of these references, the BST capacitors are fabricated on a silicon substrate. The results were good at low frequencies, i.e., about 10 megahertz; however, metal oxide thin film capacitors having high capacitance at high frequencies, i.e., at frequencies of 1 gigahertz and higher, are not easily fabricated using silicon substrates. Since, the typical operating frequencies of memories and other electronic devices is constantly increasing, such BST capacitors are becoming less and less useful for current state-of-the-art electronic devices.
It is also known that a DRAM memory containing a thin film of the metal oxide such as barium strontium titanate (xe2x80x9cBSTxe2x80x9d) in a memory capacitor can be fabricated on other semiconductor substrates also. See, for example, U.S. Pat. Nos. 5,793,057 issued Aug. 11, 1998 to Scott R. Summerfelt, No. 5,729,054 issued on Mar. 17, 1998 to Scott R. Summerfelt et al., No. 5,504,041 issued on Apr. 2, 1996 to Scott R. Summerfelt, and No. 5,473,171 Issued Dec. 5, 1995 to Scott R. Summerfelt. However, all these patents teach that either a complex underlying structure, exotic materials, or both are required to utilize the BST on any substrate. The complex underlying layers create three additional problems: they add to the expense of making the memory, and they add bulk to the memory making it difficult to create a small, dense memory package. The exotic materials Introduce new, untested materials into the integrated circuit fabrication process that can lead to further manufacturing problems and/or create compatibility problems over time. Further, while the references are silent as to the usefulness of such complex structures and exotic materials in obtaining good high frequency performance, it is evident that the complex structures create multiple capacitances in series that are generally believed to be detrimental to high frequency performance.
Thus, it would be highly desirable to have a high dielectric constant integrated circuit capacitor structure that was relatively simple, utilized conventional integrated circuit materials, and still performed well at high frequencies.
3. Solution to the Problem
The invention provides a structure and a fabrication method for high-capacitance, high-frequency thin film capacitors that avoid problems associated with prior art substrates.
The invention provides a high capacitance thin film capacitor device comprising a silicon germanium substrate (xe2x80x9cSiGe substratexe2x80x9d) and a capacitor, wherein the capacitor comprises a bottom electrode, a top electrode, and a thin film of dielectric metal oxide between the electrodes. In one embodiment of the Invention, the thin film of metal oxide comprises barium strontium titanate. The barium strontium titanate may be represented by a chemical formula (Ba1-xSrx)TiO3, where 0xe2x89xa6xxe2x89xa61, and preferably by the formula (Ba0.7Sr0.3)TiO3. In another embodiment, the metal oxide comprises a layered superlattice material. The layered superlattice material may be ferroelectric or nonferroelectric. In another embodiment, the metal oxide comprises a perovskite compound. The perovskite may be ferroelectric or nonferroelectric.
In this disclosure, the term xe2x80x9csilicon germanium (SiGe) substratexe2x80x9d is defined as any semiconductor substrate that contains a silicon germanium region. In one embodiment, the SiGe substrate comprises a silicon germanium semiconductor wafer. In this embodiment, the SiGe region essentially comprises the entire wafer. However, in a typical embodiment, the SiGe substrate comprises a conventional semiconductor silicon wafer containing a distinct silicon germanium region. In this typical embodiment, the silicon germanium region may be germanium-doped silicon, or it may be an epitaxial silicon germanium layer. An epitaxial silicon germanium layer may be deposited on silicon using conventional methods, which include molecular beam epitaxy (xe2x80x9cMBExe2x80x9d), rapid thermal chemical vapor deposition (xe2x80x9cRTCVDxe2x80x9d), and ultra-high vacuum chemical vapor deposition (xe2x80x9cUHVCVDxe2x80x9d). Typically, a silicon germanium layer on silicon is patterned and etched, or alternatively, it may be initially formed according to a pattern.
In an embodiment of the invention, the SiGe substrate comprises a silicon germanium device portion. The silicon germanium device portion includes a silicon germanium device. The silicon germanium device included in the silicon germanium device portion may be a BICMOS device. The silicon germanium device may be a heterojunction bipolar transistor (xe2x80x9cHBTxe2x80x9d) device. The silicon germanium device may be a MOSFET. At least part of the silicon germanium region is included in the silicon germanium device portion and in the silicon germanium device.
In a typical embodiment, the invention comprises a field oxide layer located on the SiGe substrate between the SiGe substrate and the bottom electrode. The field oxide layer may comprise silicon. An embodiment of the invention may comprise a diffusion barrier layer located on the field oxide layer between the field oxide layer and the bottom electrode.
The invention provides an improvement over co-pending and co-owned U.S. patent application Ser. No. 08/438,062, which is a divisional application of U.S. patent application Ser. No. 08/214,401, now U.S. Pat. No. 5,620,739. In the most preferred embodiment, a diffusion barrier layer is formed over a SiGe substrate between the substrate and the bottom electrode. The diffusion barrier layer may comprise Si3N4. When the capacitor device contains a diffusion barrier layer, it preferably also contains a stress reduction layer located on the diffusion barrier layer between the diffusion barrier layer and the bottom electrode. The stress reduction layer may comprise silicon dioxide or a glasseous oxide.
The bottom electrode of the capacitor may comprise an adhesion layer and a second, electrode layer. The adhesion layer may be a material selected from titanium, tantalum, nickel, tantalum silicide, nickel silicide, and palladium. Preferably, the electrode comprises platinum.
The invention also provides a method of fabricating a high capacitance thin film capacitor device. The method includes steps of providing a SiGe substrate; forming a bottom electrode; providing a liquid precursor for forming a thin film of dielectric metal oxide; applying the liquid precursor to form a coating on the bottom electrode; treating the coating on the bottom electrode to form the thin film of dielectric metal oxide; and forming a top electrode on the thin film of dielectric metal oxide. Preferably, the step of applying comprises spinning the liquid precursor on the bottom electrode. The step of treating typically comprises heating the coating on the electrode to a temperature of from 200xc2x0 C. to 500xc2x0 C. In particular, the step of treating may comprise heating the coating on the electrode to a temperature of about 400xc2x0 C. in air or nitrogen gas. The step of treating comprises annealing the coating on the electrode at a temperature of between 600xc2x0 C. and 850xc2x0 C. Typically, the annealing is conducted at a temperature of about 700xc2x0 C. in oxygen. Typically, the step of treating comprises a first anneal of the thin film of dielectric metal oxide for a time between 1 minute and 90 minutes. Typically, the method of the invention further includes a second anneal of the thin film of dielectric metal oxide for a time between 1 minute and 90 minutes. In an embodiment of the method, the step of treating may include drying the liquid coating, and it may further include repeating the steps of applying the liquid precursor and drying the liquid coating one or more times until the thin film of dielectric metal oxide has a desired thickness. The liquid precursor may comprise a metal carboxylate, a metal alkoxide, or a metal alkoxycarboxylate.
In an embodiment of the invention, the method preferably further comprises a step of forming a diffusion barrier layer on the substrate. Typically, the diffusion barrier layer comprises Si3N4, and the Si3N4 layer typically has a thickness of about 150 nm. The invention most preferably further includes a step of forming a stress reduction layer between the steps of forming a diffusion barrier layer and forming a bottom electrode. Typically, the stress reduction layer is silicon dioxide. The silicon dioxide layer typically has a thickness of about 100 nm.
Preferably, a relatively low temperature spin-on process as described in copending and co-owned U.S. patent application Ser. No. 08/165,082, incorporated herein by reference, is used to deposit the metal oxide.
The use of a liquid precursor spin-on process to deposit the metal oxide permits much more accurate control of the stoichiometry of the metal oxide and also results in a much more homogeneous material than achieved with other methods. This homogeneity and careful control of the drying and annealing processes leads to electronic properties which are much better than in thin film devices fabricated by prior art methods. Further, the homogeneity of the metal oxides significantly reduces the stresses and cracking that accompanied prior art fabrication methods.
Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.